Increases in device scaling and emerging chip-multi processor (CMP) architectures demand greater throughput, power consumption, and reliability from memory systems. Newer generations of dynamic random access memory (DRAM) are designed to provide higher throughput by employing n-bit prefetch and burst access capabilities combined with high-speed signaling techniques. As DRAM channel frequencies increase, adding more ranks or modules deteriorates signal integrity, which limits total memory capacity. A technique for overcoming slow memory access times involves using bank-level parallelism in which multiple memory accesses are issued to different banks of a DRAM to hide DRAM latency. As DRAM dock frequencies increase, switching ranks results in idle cycles on data buses, which introduces time delays between data outputs. This leads to undesirable bus utilization performance of DRAM data buses.